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Implementing Direct Digital Synthesizer & Low-Pass Filter on Verilog with the help of Matlab

This repository contains the code and documentation for a digital system design project implemented using MATLAB and Verilog. The project focuses on designing and implementing a FIR (Finite Impulse Response) Low Pass Filter (LPF) within the context of a Digital Signal Synthesizer (DDS).

Direct Digital Synthesizer Architecture Proposal

Figure 1: Direct Digital Synthesizer Architecture Proposal

Direct Digital Synthesizer Architecture realization in Verilog

Figure 2: Direct Digital Synthesizer Architecture realization in Verilog

Overview

The project involves the following components:

  • System Architecture: The architecture of the digital system, including the data path, control path, and top-level system design.

  • Filter Design in MATLAB: Designing a FIR LPF using MATLAB's Filter Designer tool, specifying frequency requirements and obtaining filter coefficients.

  • Filter Implementation in Verilog: Implementing the FIR LPF in Verilog, integrating it into the larger DDS system architecture.

  • Verification and Simulation: Validating the Verilog implementation through simulation and comparing results with MATLAB's ideal plots.

Usage

To reproduce the results or run simulations:

  1. Navigate to the relevantS Source code repositories to get the source codes..
  2. You can follow the instructions in the provided documents/reports in this repository, which gives an overview of each step taking in this project.
  3. Execute the scripts or commands as instructed to run simulations, generate plots, or analyze results.

License

This project is licensed under the GNU License.