Bachelor thesis at the Technical University of Munich with the titel 'Extending the RISC-V Memory Management Unit by Support for a Real-Time Capable Checkpoint/Restore Mechanism'
Modern processors are used in nearly every application today, and they are gettingmore and more important. User depend increasingly on the correct function of modernmachines. The software of a self-driving car, for example, is a very critical applicationthat should not completely crash. The same holds for modern medical devices andother mission-critical appliances. To reduce the impact of hardware failures and otherunforeseen events systems are build with redundant hardware. In the case of failure,the redundant part of the system can take over. Depending on the system this step cantake valuable time, as the system needs to initialize and boot up to the state where theprevious system has failed. Checkpoint/Restore mechanisms are put in place to reducethe impact of such defects further, as a checkpointed system only loses the progresssince the last checkpoint in case of a crash.As most of the current Checkpoint/Restore mechanisms are implemented in software,they introduce certain bottlenecks into the system. Especially the tracking of changesto checkpointed memory and the copying of such memory to conserve previous stateshas proven to be costly. The most currently available hardware merely is not madewith Checkpoint/Restore systems in mind. To accelerate critical systems hardwareacceleration have since been used. Hardware modules that are connected over thesystem bus or other connections might not be fast enough for high-speed systems.Thus this thesis will look in the possibility to directly modify components in the CPUto accelerate Checkpoint/Restore algorithms further. To freely modify a CPU, oneneeds an open CPU architecture. In this thesis, the upcoming RISC-V instruction setarchitecture was chosen as it looks promising and can be freely obtained. The RISC-VISA is a free blueprint of a processor architecture and was initially developed by theUniversity of California, Berkeley. As for the implementation part of this thesis, we willuse three kinds of Xilinx FPGA boards, the included development suite Xilinx Vivadoand the RISC-V implementation Rocket Chip as it appears to be the most popular RISC-V project as of the time of this thesis. Later this thesis will present a Checkpoint/Restoremechanism that builds on the modification of the memory management unit (MMU) inthe CPU. We will explore how the Rocket Chip project has integrated the MMU in theirRocket cores and how we could apply the proposed concept. Due to time constraints,the concept could not be implemented.