How to generate memory model correctly?

[whutddk]

When I instance an SRAM, I want it compiles into a separate Verilog behavior model. And I used --gen-mem-verilog ShellOption. But I found it difficult to compile into the SRAM style that I wanted.

我想将我的SRAM在编译为Verilog时单独抽出为行为模型文件，我用了 --gen-mem-verilog 命令行选项。但我发现很难如愿获得所需SRAM类型。

When I used Mem and added a register at the data output port, it never generated a separate Verilog Behavior model.

如果我用Mem来例化并在输出手动添加寄存器，好像并不能识别并产生行为模型文件。

When I used SyncReadMem in a separate file, like this, a combination loop will be detected by mistake between io.enw and io.datar, due to the outer logic.

如果我在单独文件中使用SyncReadMem来例化，如下代码所示，编译过程中将因为外部逻辑中io.enw与io.datar的关系错误地产生组合逻辑环错误。

It's a recommended usage for single-port SRAM in chisel-lang, but it makes me confused, what io.datar will behave in when? Is it a wire or a register?

这是chisel-lang中对于单端口SRAM的推荐写法。但对于 io.datar在when语法块中的行为让我很迷惑，它作为output应该是wire型，但在when中却产生了寄存器的行为。

class DTagRAM(implicit p: Parameters) extends DcacheModule {
  val io = IO(new Bundle{
    val addr  = Input(UInt(line_w.W))

    val dataw = Input( UInt(tag_w.W) )
    val datar = Output( UInt(tag_w.W) )
    val enw   = Input(Bool())
    val enr   = Input(Bool())
  })

  val dTagMem = SyncReadMem( cl, UInt(tag_w.W) )


  io.datar := DontCare
  when( io.enw ) {
    dTagMem.write( io.addr, io.dataw )
  } .otherwise {
    io.datar := dTagMem.read( io.addr )
  }

}

Then I try another coding style like this: I found that the combination loop will not detect but I got a dual-port SRAM Verilog Behavior model instead. But I need a single-port SRAM.

之后我调整了代码，将io.enr作为条件从而避免了组合逻辑环，但是编译得到的是双端口SRAM，事实上我只能在一个干净工程中产生单端口SRAM, 在当前工程中从没成功过。

class DTagRAM(implicit p: Parameters) extends DcacheModule {
  val io = IO(new Bundle{
    val addr  = Input(UInt(line_w.W))

    val dataw = Input( UInt(tag_w.W) )
    val datar = Output( UInt(tag_w.W) )
    val enw   = Input(Bool())
    val enr   = Input(Bool())
  })

  val dTagMem = SyncReadMem( cl, UInt(tag_w.W) )

  io.datar := DontCare
  when( io.enr ) {
    io.datar := dTagMem.read( io.addr )
  } .elsewhen( io.enw & ~io.enr ) {
    dTagMem.write( io.addr, io.dataw )
  }
}

So I want to know if there is a recommended usage to instant SRAM, and compile to the Verilog Behavior model correctly.
Or maybe we need more API to instant SRAM in different styles?

所以我想知道是否有产生SRAM Verilog 行为模型文件的推荐写法，或者我们需要实现其他API来产生不同类型的SRAM。