feature request: constant folding for division and remainder

[ekiwi]

Feature Description

If there is a division or a remainder operation where both arguments are constant, the firrtl compiler should replace it with a constant.

Type of Feature

• better optimization

[seldridge]

Agree.

Small example of this:

circuit Foo :
  module Foo :
    output out : UInt<32>

    node _out_T = div(UInt<6>("h21"), UInt<3>("h4"))
    out <= _out_T 

This produces the following Verliog:

module Foo(
  output [31:0] out
);
  wire [5:0] _out_T = 6'h21 / 3'h4;
  assign out = {{26'd0}, _out_T};

It should produce:

module Foo(
  output [31:0] out);

  assign out = 32'h8;
endmodule

This is a situation where CIRCT has the optimization, but Scala FIRRTL does not. (I used it to generate the bottom Verilog.)