Disable SV generation when running VHDL code generation

[SzymonHitachi]

Hi, Is there any way to disable SV code generation when running VHDL plugin and generate VHDL code only?

[taichi-ishitani]

Hi @SzymonHitachi ,
You can use --enable option for this purspose.

$ rggen -c config.yaml --enable vhdl regmap.yaml

For this example, RgGen will generate VHDL only.

$ rggen -c config.yaml --enable vhdl,markdown,c_header regmap.yaml

For this example, RgGen will generate VHDL, Markdown and C header files.

[SzymonHitachi]

Thanks, that is what I was looking for

[SzymonHitachi]

As a general comment: It would be amazing if all the configurations would come from same spot (e.g. the config file) instead of some from CLI and some from yaml

[taichi-ishitani]

Thank you for your feedback!
The --enable and --output CLI switches can be moved to the config file.