An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
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Updated
Mar 11, 2019 - C++
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
Predicting 3D human pose from single image using a VCK5000 Versal Development Card
TURBOdeb #xohw19-157 #TuringBombe #Enigma
🏄 Custom IP for vector operations
A lightweight cloudFPGA prototype for processor simulation. It provides online scalable route resources with only open source synthesis toolset.
Develop DMA acceleration of the system that performs linear computing functions, Y = AX + B, large amounts of data.
HLS-based framework to accelerate the implementation of 2-D DP kernels on FPGA
Janus astrophysics Simulator implemented on ZU19EG Ultrascale+
A framework for Automated Design Space Exploration
Smart Automation Controller for Precision Agriculture
University of Pittsburgh ECE 1195
An FPGA design for simulating biological neurons
Blake2 RTL implementation
Janus Algorithm in C++ version without FPGA acceleration.
FPGA with Xilinx Vitis HLS and ZYNQ board. AXI and VHDL: Simple Multiplier, AXI and VHDL: DoGain
This repository contains the design and implementation of a Spiking Neural Network (SNN) Processor. Spiking Neural Networks are a biologically-inspired class of artificial neural networks, where neurons communicate by sending discrete spikes.
Projekt zaliczeniowy w ramach przedmiotu "Systemy Cyfrowe". Projekt miał na celu stworzenie układu DSP do pomiaru odległości za pomocą odbitego światła lasera. Wykonano układ który można finalnie uruchomić na płytce Cyclone IV Altera (model EP4CE6E22), który można sterować bezpośrednio na płytce. Objaśnienie projektu znajduje się w załączonym do…
FPGA with Xilinx Vitis HLS, Vivado, Vitis, and ZYNQ board. Working with HLS, Matrix Multiplier with HLS
EXPERIMENTAL Verilog (and HLS, C++, Python, OpenCL) implementation of the RC4 stream cipher.
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