A 16-bit RISC processor core model in VHDL. All including components and testbenches tested on both Xilinx and Altera boards.
The project includes the following subprojects (in various implementation variations), each of which is part of the final processor core:
- Arithmetic Logic Unit (LSM)
- Interrupt Controller Type Register (ICTR)
- Random Access Memory (RAM)
- Registers-based RAM e.g. Fast Memory (FM)
- Multiplication Unit (MPU) with Local State Machine (LSM)
- Arithmetic Unit with Microprogram Control
- Central Processing Unit (CPU)
Auto-generation electrical circuits are present inside projects.
RAM:
FM:
MPU with FSM:
AU with Microprogram Control:
CPU:
