Second Year Computer Engineering Undergraduate at the University of Peradeniya.
-
University of Peradeniya
- Kurunegala, Sri Lanka
- in/Bimsara-Janakantha
Highlights
- Pro
Pinned Loading
-
8-Bit-Single-Cycle-Processor
8-Bit-Single-Cycle-Processor PublicA simple single cycle processor using Verilog HDL
Verilog
-
SAP-1_Computer_ALU_Design
SAP-1_Computer_ALU_Design PublicImplementation of the Arithmetic Logic unit of the SAP1 computer, a minimalist educational computer architecture, for the CO221 course project at Department of Computer Engineering - University of …
C++
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.