Skip to content
View CodeWithAbbas's full-sized avatar
  • Electrical Engineering From UET
  • Peshawar

Block or report CodeWithAbbas

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
CodeWithAbbas/README.md
  • 👋 Hi, I’m @CodeWithAbbas

"Hello! I'm an FPGA engineer passionate about embedded systems, especially Microcontrollers and FPGAs. Proficient in HDL (Verilog/VHDL) and experienced with Vivado and Quartus Software, I'm eager to collaborate on FPGA algorithms. Together, let's explore the possibilities of FPGA technology. Feel free to reach me at 18jzele0237@uetpeshawar.edu.pk for collaboration opportunities."

Pinned Loading

  1. FPGA-Designing FPGA-Designing Public

    It contains the VHDL coding of basic combinational and sequential circuits as well as top level design including Datapath and Controller