forked from YosysHQ/yosys
-
Notifications
You must be signed in to change notification settings - Fork 41
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
bump fork for version 0.44 #23
Merged
Merged
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Avoid building a cell-to-inbit map when sorting the cells, add a warning if we are unable to sort, and move the code treating non-combinational cells ahead of the rest (this means we don't need to pass non-combinational cells to the TopoSort object at all).
Each call to `handle_clkpol_celltype_swap` has a conversion of the cell's type ID to an allocated string. This can sum up to a non-negligible time being spent in the clkpol code even for a design which doesn't have any flip-flop gates.
* Add some primes as suggested in #4458. This allows larger hashtables to be allocated for very big designs
changes made to filenames + references
Move tests
add missing INIT for uSRAM
We add a BANDGAP primitive used to turn off power to OSC, PLL and other things on some GOWIN chips. We also mark this primitive and GSR as keep. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* area should be 1 for all LUTs * clean up macros * add log_assert to fail noisily when encountering oddly configured DFF * clean help msg * flatten set to true by default * update * merge mult tests * remove redundant test * move all dsp tests to single file and remove redundant tests * update ram tests * add more dff tests * fix c++20 compile errors * add option to dump verilog * default to use abc9 * remove -abc9 option since its the default now --------- Co-authored-by: tony <minchunlin@gmail.com>
Guess VHDL frontend for both *.vhd and *vhdl files
synthprop: Reformat the help
The text starting at line 118 refers to proc twice but it should refer to opt and then to proc.
Update interactive_investigation.rst
sigmap: comments
…min_cost parameter
proc_rom: test src attribute on memories
hashlib: Add some more primes
Release build configuration improvements
Initialize extensions when Verific pass is registered
Add PolarFire FPGA support
cost: add keep_hierarchy pass with min_cost argument
VHDL is case insensitive, make sure netlist name is proper
Set ranges on exported wires in VCD and FST
Makefile: no LTO and lld by default
eder-matheus
merged commit Aug 6, 2024
cd29229
into
The-OpenROAD-Project:master
16 of 17 checks passed
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
No description provided.