These projects are from my course work and independent study during my MS degree.
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Purdue University
- Indianapolis,IN
- https://www.linkedin.com/in/aviyadavpurdue/
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StaticTimingAnalysis
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WallaceTreeMultiplier
WallaceTreeMultiplier PublicFull Custom Design of 5-bit x 5-bit Multiplier Circuit
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CarryRipppleAdderWithFlags PublicASIC implementation of 64-bit CRA with flags
Verilog
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