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Add remaining opcodes
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Rexagon committed Sep 9, 2023
1 parent 001bdfc commit 515599b
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Showing 2 changed files with 53 additions and 1 deletion.
8 changes: 8 additions & 0 deletions libs/src/Asm.fif
Original file line number Diff line number Diff line change
Expand Up @@ -1154,6 +1154,10 @@ x{F4BF} @Defop DICTUGETEXECZ

x{F800} @Defop ACCEPT
x{F801} @Defop SETGASLIMIT
x{F802} @Defop BUYGAS
x{F804} @Defop GRAMTOGAS
x{F805} @Defop GASTOGRAM
x{F806} @Defop GASREMAINING
x{F80F} @Defop COMMIT

x{F810} @Defop RANDU256
Expand All @@ -1169,6 +1173,10 @@ x{F826} @Defop RANDSEED
x{F827} @Defop BALANCE
x{F828} @Defop MYADDR
x{F829} @Defop CONFIGROOT
x{F82A} @Defop MYCODE
x{F82B} @Defop INITCODEHASH
x{F82C} @Defop STORAGEFEE
x{F82D} @Defop SEQNO
x{F830} @Defop CONFIGDICT
x{F832} @Defop CONFIGPARAM
x{F833} @Defop CONFIGOPTPARAM
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46 changes: 45 additions & 1 deletion src/modules/vm_utils.rs
Original file line number Diff line number Diff line change
Expand Up @@ -74,6 +74,7 @@ fn cp0() -> &'static DispatchTable {
register_continuation_ops(&mut t)?;
register_dictionary_ops(&mut t)?;
register_ton_ops(&mut t)?;
register_debug_ops(&mut t)?;
register_codepage_ops(&mut t)?;
Ok(t.finalize())
}
Expand Down Expand Up @@ -644,6 +645,10 @@ fn register_ton_ops(t: &mut OpcodeTable) -> Result<()> {
// Basic gas
t.add_simple(0xf800, 16, "ACCEPT")?;
t.add_simple(0xf801, 16, "SETGASLIMIT")?;
t.add_simple(0xf802, 16, "BUYGAS")?;
t.add_simple(0xf804, 16, "GRAMTOGAS")?;
t.add_simple(0xf805, 16, "GASTOGRAM")?;
t.add_simple(0xf806, 16, "GASREMAINING")?;
t.add_simple(0xf80f, 16, "COMMIT")?;

// PRNG
Expand All @@ -661,7 +666,11 @@ fn register_ton_ops(t: &mut OpcodeTable) -> Result<()> {
t.add_simple(0xf827, 16, "BALANCE")?;
t.add_simple(0xf828, 16, "MYADDR")?;
t.add_simple(0xf829, 16, "CONFIGROOT")?;
t.add_fixed_range(0xf82a, 0xf830, 16, 4, dump_1c("GETPARAM "))?;
t.add_simple(0xf82a, 16, "MYCODE")?;
t.add_simple(0xf82b, 16, "INITCODEHASH")?;
t.add_simple(0xf82c, 16, "STORAGEFEE")?;
t.add_simple(0xf82d, 16, "SEQNO")?;
t.add_fixed_range(0xf82e, 0xf830, 16, 4, dump_1c("GETPARAM "))?;
t.add_simple(0xf830, 16, "CONFIGDICT")?;
t.add_simple(0xf832, 16, "CONFIGPARAM")?;
t.add_simple(0xf833, 16, "CONFIGOPTPARAM")?;
Expand Down Expand Up @@ -713,6 +722,14 @@ fn register_ton_ops(t: &mut OpcodeTable) -> Result<()> {
Ok(())
}

#[rustfmt::skip]
fn register_debug_ops(t: &mut OpcodeTable) -> Result<()> {
t.add_fixed_range(0xfe00, 0xfef0, 16, 8, dump_1c_and(0xff, "DEBUG "))?;
t.add_ext(0xfef, 12, 4, Box::new(dump_dummy_debug_str), Box::new(compute_len_debug_str))?;

Ok(())
}

fn register_codepage_ops(t: &mut OpcodeTable) -> Result<()> {
t.add_fixed_range(0xff00, 0xfff0, 16, 8, dump_1c_and(0xff, "SETCP "))?;
t.add_fixed_range(0xfff1, 0x10000, 16, 8, dump_1c_l_add(-256, "SETCP "))?;
Expand Down Expand Up @@ -1554,6 +1571,33 @@ fn compute_len_push_slice_ext(cs: &CellSlice<'_>, slice_len: (u16, u8), bits: u1
}
}

fn dump_dummy_debug_str(
cs: &mut CellSlice<'_>,
args: u32,
bits: u16,
f: &mut dyn std::fmt::Write,
) -> Result<()> {
let slice_bits = ((args as u16 & 0xf) + 1) * 8;
if !cs.has_remaining(bits + slice_bits, 0) {
return Ok(());
}
cs.try_advance(bits, 0);
let mut slice = cs.get_prefix(slice_bits, 0);
cs.try_advance(slice_bits, 0);
slice_trim_end(&mut slice)?;

write!(f, "DEBUGSTR x{}", slice.display_data())?;
if !slice.is_refs_empty() {
write!(f, ",{}", slice.remaining_refs())?;
}
Ok(())
}

fn compute_len_debug_str(cs: &CellSlice<'_>, args: u32, bits: u16) -> (u16, u8) {
let bits = bits + ((args as u16 & 0xf) + 1) * 8;
(bits * cs.has_remaining(bits, 0) as u16, 0)
}

fn dump_store_int_var(_: &mut CellSlice<'_>, args: u32, f: &mut dyn std::fmt::Write) -> Result<()> {
let signed = if args & 0b001 != 0 { "I" } else { "U" };
write!(f, "ST{signed}X")?;
Expand Down

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