fix: fix wrong mill source layout · chipsalliance/chisel@99a6144

Triggered via pull request November 16, 2024 13:23

unlsycn

synchronize #4511

Status Success

Total duration 21m 57s

Artifacts 2

ci.yml

on: pull_request

Matrix: ci

Produced during runtime

Name	Size
chisel-example.scala	731 Bytes
website	8.9 MB