UART Interface in VHDL. Constraints for Zybo Z7
To have a brief understanding of UART protocol: https://www.analog.com/en/analog-dialogue/articles/uart-a-hardware-communication-protocol.html
FIFO structure stores and shifts packages at every one-clock pulse of wr_uart or rd_uart. The file register's depth and width can be adjusted in generic parameters
wr_uart: enables writing mode(stores into fifo_tx), wr_data(parallel bus) will be reflected at tx(serial) pin. Just one-clock pulse per bit package
rd_uart: enables reading mode(shifts fifo's stored packages), rx(serial) will be reflected at rd_data bus (parallel). Just one-clock pulse per byte package
rx_empty: signal flag, high when fifo_rx is empty
rx_empty: signal flag, high when fifo_tx is full