codec timings reduced for unoptimized code

monome · Jul 11, 2024 · bd91256 · bd91256
1 parent 15d9604
commit bd91256
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Showing 5 changed files with 49 additions and 3 deletions.
diff --git a/lib/sfold.c b/lib/sfold.c
@@ -52,10 +52,20 @@ void sfold_set_id(float i){
 
 // separate run function per channel
 // returns 0..1
+static float phasor = 0.f;
+static float pinc = 100.f / (2.f * 6000.f); // are we running twice per frame?
 float sfold(int channel){
     // OFFSET
     float retval = offset;
 
+    // tmp: sawtooth oscillator
+    // float retval = phasor;
+    // if(channel == 0){
+    //     phasor += pinc; 
+    //     if(phasor>=1.f) phasor -= 1.f;
+    // }
+
+
     // ROTATE
     // create rotated_index by adding ROTATE to channel index
     float rix = (float)channel + ((rotate - 0.5f) * _ch); // allows rotate to perform 360

diff --git a/ll/adc.c b/ll/adc.c
@@ -41,8 +41,8 @@ void ADC_Init(void){
     }
 
     // Channel configuration
-    sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES;
-    // sConfig.SamplingTime = ADC_SAMPLETIME_144CYCLES;
+    // sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES;
+    sConfig.SamplingTime = ADC_SAMPLETIME_144CYCLES;
     sConfig.Offset       = 0;
 
     sConfig.Channel      = ADC_CHANNEL_7;
@@ -237,14 +237,17 @@ void DMA2_Stream2_IRQHandler(void){
     HAL_DMA_IRQHandler(AdcHandle2.DMA_Handle);
 }
 
+static int counter = 0;
 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc){
+    counter++;
     if(hadc == &AdcHandle){
         read_half[0] = 0;
     } else if(hadc == &AdcHandle2){
         read_half[1] = 0;
     }
 }
 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc){
+    counter++;
     if(hadc == &AdcHandle){
         read_half[0] = 1;
     } else if(hadc == &AdcHandle2){
@@ -254,3 +257,10 @@ void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc){
 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc){
     Caw_printf("adc error\n\r");
 }
+
+// debug / timing / optimization
+int ADC_get_count(void){
+    int c = counter;
+    counter = 0;
+    return c;
+}
diff --git a/ll/adc.h b/ll/adc.h
@@ -21,3 +21,5 @@ void DMA2_Stream2_IRQHandler(void);
 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+
+int ADC_get_count(void);
diff --git a/ll/dac108.c b/ll/dac108.c
@@ -178,13 +178,36 @@ static void sai_init(void){
     rcc.PeriphClockSelection    = RCC_PERIPHCLK_SAI2;
     rcc.Sai2ClockSelection      = RCC_SAI2CLKSOURCE_PLLSAI;
 
+    // 30MHz maximum bit clock in daisy-chain mode
+    // every 2 channels takes 33 clks
+    // for 16 channels, that's 528 clks
+    // at 30MHz (max) that's 56,818Hz
+    // 48kHz -> 25,344,000 core clock
+
+
     // here we configure for 3.072MHz
     // ie 8 channels, 17bits, 22.5kHz sample rate
     // rcc.PLLSAI.PLLSAIN          = 384;
     // rcc.PLLSAI.PLLSAIN          = 192;
-    rcc.PLLSAI.PLLSAIN          = 96;
+
+    // 6kHz
+    rcc.PLLSAI.PLLSAIN          = 396;
     rcc.PLLSAI.PLLSAIQ          = 5;
     rcc.PLLSAIDivQ              = 25;
+
+    // 24kHz
+    // rcc.PLLSAI.PLLSAIN          = 431;
+    // rcc.PLLSAI.PLLSAIQ          = 2;
+    // rcc.PLLSAIDivQ              = 17;
+
+    // 48kHz
+    // rcc.PLLSAI.PLLSAIN          = 380;
+    // rcc.PLLSAI.PLLSAIQ          = 3;
+    // rcc.PLLSAIDivQ              = 5;
+
+    // rcc.PLLSAI.PLLSAIN          = 96;
+    // rcc.PLLSAI.PLLSAIQ          = 5;
+    // rcc.PLLSAIDivQ              = 25;
     // see @ciel/tools/sai_pll_calculator.lua to configure
 
     HAL_RCCEx_PeriphCLKConfig(&rcc);

diff --git a/main.c b/main.c
@@ -103,6 +103,7 @@ int main(void){
                 a >>= 12; // divide by 4096
                 lights_xset(stepped_ix());
                 // Caw_printf("%i\n\r",a);
+                Caw_printf("%i\n\r",ADC_get_count());
             }
             for(int i=0; i<6; i++){
                 // ADDA_set_val(i, ADC_get(i));