Must-have verilog systemverilog modules
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Updated
Nov 7, 2024 - Verilog
Must-have verilog systemverilog modules
An abstraction library for interfacing EDA tools
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
All open source file and project for OpenFPGAduino project
Docs, design, firmware, and software for the Haasoscope
DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on.
🏧 Second life for FPGA boards which can be repurposed to DYI/Hobby projects ...............................................................................................
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
usb-jtag - Altera USB Blaster Emulation with a FX2
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
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