This experiment belongs to VLSI Lab IIITH. Name: Delay Estimation In Chain Of Inverters

This experiment belongs to VLSI Lab IIITH. Name: Schematic Design Of Transistor Level NAND & NOR Gate

This experiment belongs to VLSI Lab IIITH. Name: Design Of D-Flip Flop Using Verilog

This experiment belongs to VLSI Lab IIITH. Name: Schematic Design Of D-Latch and D-Flip Flop

This experiment belongs to VLSI Lab IIITH. Name: Design Of Digital Circuits Using Verilog

This experiment belongs to VLSI Lab IIITH. Name: Schematic Design Of Transistor Level XOR & XNOR Gate

This experiment belongs to VLSI Lab IIITH. Name: Schematic Design Of Pass Transistor Logic & Multiplexer

This experiment belongs to VLSI Lab IIITH. Name: Spice Code Platform

This experiment belongs to VLSI Lab IIITH. Name: Layout Design

This experiment belongs to VLSI Lab IIITH. Name: Schematic Design Of Transistor Level Inverter

This repository contains sources for VLSI lab