RISC-V CPU implementation in Amaranth HDL (aka nMigen)
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Updated
Aug 27, 2024 - Python
RISC-V CPU implementation in Amaranth HDL (aka nMigen)
windows builds of wch openocd fork
A template for running jtag_vpi simulations in vcs
Openocd for WCH-LinkE with support for multi-WCHLinkE debugging
Example project CLion + OpenOCD + Raspberry PI W Zero as OTA flashing probe + Longan Nano(Risc-V) demo board
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