Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.
polito
vhdl
scripts
tcl
rtl
verilog
synthesis
digital-design
control-unit
subtractor
physical-design
booth-multiplier
register-file
windowed-register-file
adder-subtractor
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Updated
Jan 24, 2021 - Verilog