Trigger Polling Interval and Digital Pins Bug Fixed

• In st.cmd user now has to define the trigger polling interval. This way, we can free the CPU core running the data acquisition thread while waiting for the trigger. This is mainly important for when some time might pass between the arming and the trigger.
• Fixed a bug where by setting the state of P digital pin, in the driver N digital pin with the same number was being set.

FPGA Reset on IOC Shutdown and Bug Fixes

Bugs fixed:

• Burst configuration is now correctly applied to each channel
• On IOC shutdown, FPGA is reset to its previous state and resources are released
• Reset and release have been moved to the asyn shutdown hook from driver's destructor

Data acquisition and generation support

• Added support for signal generation
• Trigger source can now be changed while we're waiting for the trigger from the device
• Renamed almost all PVs to make them shorter and consistent
• Updated documentation

Data acquisition support

Support for fast data acquisition and analogue and digital in/outs.