simple verilog digital circuits sampels (halfAdder, fullAdder, ALSU , ...)

These are VHDL codes for a signed 4bit multiplier using 4bit adders. Base on Baugh-Wooley Method.

Hardware Simulation using Icarus Verilog EDA Playground for a half adder circuit design and test bench.

Some logic circuits for studies and reviews

A half adder is a digital circuit that performs addition of two binary digits, generating the sum bit and the carry bit.

The computational speed of the dadda multiplier can be enhanced by partitioning the partial products. In process to achieve low power we have considered pass transistor for logical implementation.

VHDL homework from FH Technikum Wien Master Embedded Systems course VHDL

Learned as a part of CS210 course