VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes contro…

RTL Design Using Verilog with SKY130nm Technology

Physical Design of Mixed Signal Circuit that performs - "Post-Layout: OpenFASOC flow for 3-bit Flash ADC using TIQ comparator".

Physical Design of Mixed signal circuit that performs- "In Memory logic using 8TSRAM cells" using OPENFASOC.

This Repo is to demonstrate RTL to GDSII design implementation

Database implementation for boutique.