An automatic schematic generation tool which generates schematics from a SPICE netlist, usually of output from qflow.

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes contro…

32-bit RISC-V microcontroller

The repository shows the 5 - day wrokshop for beginners using open source tools like yosys, magic, opentimer, qrouter and the purpose of this repository is to provide a complete idea about the 5 - days workshop on VLSI SoC/Physical design using open source EDA tools.

RTL to GDS II flow for a custom "Oven FSM" ASIC design utilising Qflow, an Open Source Physical Design toolchain.

Here you can find different verifications, time analysis, etc.

6-bit prefix adder implemented via Verilog HDL.