verilog-hdl

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 7…

verilog verilog-hdl miniproject verilog-project

Updated Nov 13, 2024
Verilog

NNgen / nngen

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NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

python deep-learning neural-network compiler hardware verilog-hdl pyverilog high-level-synthesis onnx veriloggen

Updated Oct 17, 2023
Python

PyHDI / veriloggen

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Veriloggen: A Mixed-Paradigm Hardware Construction Framework

python compiler hardware verilog-hdl pyverilog high-level-synthesis hardware-construction-language

Updated Aug 10, 2024
Python

mshr-h / vscode-verilog-hdl-support

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HDL support for VS Code

ctags vscode verilog vivado systemverilog icarus-verilog modelsim hacktoberfest verilog-hdl iverilog bluespec-systemverilog verilator language-server-client systemverilog-support svls

Updated Nov 14, 2024
TypeScript

dpretet / async_fifo

Sponsor

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A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain

Updated Apr 30, 2024
Verilog

ultraembedded / core_jpeg

Sponsor

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High throughput JPEG decoder in Verilog for FPGA

fpga mjpeg verilog motion-jpeg verilog-hdl jpeg-decoder axi-stream

Updated Mar 5, 2022
Verilog

Gowtham1729 / Image-Processing

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Image Processing Toolbox in Verilog using Basys3 FPGA

Updated Sep 19, 2023
VHDL

AUCOHL / Fault

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A complete open-source design-for-testing (DFT) Solution

testing dft eda verilog verilog-hdl jtag atpg fault-simulation vlsi-cad scan-chains stuck-at

Updated Nov 2, 2024
Swift

thedatabusdotio / fpga-ml-accelerator

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This repository hosts the code for an FPGA based accelerator for convolutional neural networks

asic fpga hardware vhdl verification verilog-hdl digital-design

Updated Jun 20, 2024
Verilog

neelkshah / MIPS-Processor

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5-stage pipelined 32-bit MIPS microprocessor in Verilog

verilog microprocessor computer-architecture microprocessors verilog-hdl mips-architecture mips-processor bits-pilani computer-organization verilog-components verilog-snippets mips-instructions computer-organisation verilog-programs verilog-simulator verilog-project

Updated Apr 3, 2020
Verilog

ben-marshall / uart

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A simple implementation of a UART modem in Verilog.

fpga hardware verilog uart uart-verilog verilog-hdl

Updated Nov 10, 2021
Verilog

aptx1231 / BUAA_CO

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2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)

mips verilog-hdl buaa buaa-co computer-organization-lab

Updated May 26, 2019
Verilog

snbk001 / Verilog-Design-Examples

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Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous F…

verilog testbenches verilog-hdl verilog-programs verilog-project verilog-code verilog-design self-checking