A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".

🤖 SoCFPGA: Open-Source Embedded Linux Distribution with a highly flexible build system, developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)

Yocto Project BSP meta-layer for Intel (ALTERA) SoC-FPGAs (SoCFPGA) - with step by step guide

IntelFPGA configuration & Avalon-MM access library for FlashAir

Demonstration how to build a Management Web interface to interact with the FPGA fabric and change the FPGA configuration with the Django Framework

High-Level Synthesis with Partial Evaluation

A Comprehensive Dataflow Compiler for High-Level Synthesis

Script to build the bootloader (u-boot) and bring all components to a bootable image for Intel (ALTERA) SoC-FPGAs

Automatically create a NIOS II Eclipse Project with the latest FreeRTOS Version, the Intel hwlib and more...

Source Code of Yocto Layer for accessing FPGA Manager of the Intel (ALTERA) Arria 10 SX SoCFPGA

Source Code of Yocto Layer for accessing FPGA Manager of the Intel (ALTERA) Cyclone V SoCFPGA

Fletcher Open Programmable Acceleration Engine platform support

Load vs Store comparison on Intel FPGA using oneAPI

SoC and Embedded Linux

OpenCL wrapper for Intel's unique chip ID function built for the Cyclone V chip on the DE1-SoC board

Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator

Play and learn with the Terasic DE0-Atlas/Nano-SoC Kit featuring a Altera/Intel Cyclone V 5CSEMA4U23C6N FPGA with integrated dual-core ARM Cortex-A9.